Fasahar marufi shine ɗayan mahimman matakai a cikin masana'antar semiconductor. Dangane da siffar kunshin, ana iya raba shi zuwa fakitin soket, fakitin Dutsen saman, kunshin BGA, kunshin girman guntu (CSP), fakitin guntu guda ɗaya (SCM, rata tsakanin wayoyi akan allon da aka buga (PCB) da matches na allon da'ira (IC)), kunshin nau'ikan guntu da yawa (MCM, wanda zai iya haɗa kwakwalwan kwamfuta daban-daban), fakitin matakin wafer (WLP, gami da fakitin matakin wafer-fita (FOWLP), micro surface abubuwan hawa (microSMD), da dai sauransu), fakitin girma uku (kunshin haɗin haɗin micro bump, fakitin haɗin haɗin gwiwar TSV, da sauransu), fakitin tsarin (SIP), tsarin guntu (SOC).
Siffofin marufi na 3D galibi sun kasu kashi uku: nau'in binne (binne na'urar a cikin wayoyi masu yawa ko binne a cikin ma'auni), nau'in substrate mai aiki (haɗin wafer silicon: da farko haɗa abubuwan da keɓaɓɓun da wafer substrate don samar da substrate mai aiki. ; sannan shirya layin haɗin haɗin da yawa, kuma tara wasu kwakwalwan kwamfuta ko abubuwan da aka yi a saman (silicon wafered tare da silicon wafers, kwakwalwan kwamfuta stacked da silica wafers, da kuma kwakwalwan kwamfuta toshe tare da kwakwalwan kwamfuta).
Hanyoyin haɗin 3D sun haɗa da haɗin waya (WB), guntu guntu (FC), ta hanyar silicon via (TSV), jagoran fim, da dai sauransu.
TSV yana gane haɗin kai tsaye tsakanin kwakwalwan kwamfuta. Tunda layin haɗin kai tsaye yana da mafi guntu nisa da ƙarfi mafi girma, yana da sauƙin gane miniaturization, babban yawa, babban aiki, da fakitin tsarin multifunctional iri-iri. A lokaci guda kuma, yana iya haɗa kwakwalwan kwamfuta na kayan daban-daban;
a halin yanzu, akwai nau'ikan fasahar masana'anta na microelectronics guda biyu ta amfani da tsarin TSV: marufi mai girma uku (haɗin 3D IC) da marufi na silicon mai girma uku (3D Si haɗin kai).
Bambancin da ke tsakanin sifofin biyu shine:
(1) Marufi na kewayawa na 3D yana buƙatar shirya na'urorin lantarki na guntu zuwa cikin bumps, kuma bumps suna haɗuwa da juna (haɗe ta hanyar haɗin gwiwa, fusion, walda, da sauransu), yayin da marufi na silicon 3D shine haɗin kai tsaye tsakanin kwakwalwan kwamfuta (haɗin kai tsakanin oxides da Cu). - Ku bonding).
(2) Za'a iya samun fasahar haɗin kai ta 3D ta hanyar haɗin kai tsakanin wafers (kwal ɗin da'irar 3D, 3D silicon packaging), yayin da haɗin guntu-zuwa-guntu da haɗin guntu-zuwa-wafer za a iya samu ta hanyar marufi na kewayen 3D kawai.
(3) Akwai rata tsakanin kwakwalwan kwamfuta da aka haɗa ta hanyar tsarin marufi na 3D, kuma kayan aikin dielectric suna buƙatar cikawa don daidaita yanayin haɓakar thermal da haɓakar haɓakar thermal na tsarin don tabbatar da kwanciyar hankali na kayan aikin injiniya da lantarki na tsarin; babu wani rata tsakanin kwakwalwan kwamfuta da aka haɗa ta hanyar tsarin marufi na siliki na 3D, kuma amfani da wutar lantarki, ƙarar, da nauyin guntu ƙananan ƙananan ne, kuma aikin lantarki yana da kyau.
Tsarin TSV zai iya gina hanyar sigina ta tsaye ta hanyar ma'auni kuma ya haɗa RDL a sama da ƙasa na substrate don samar da hanyar jagora mai girma uku. Sabili da haka, tsarin TSV yana ɗaya daga cikin mahimman ginshiƙai don gina tsarin na'ura mai ma'ana guda uku.
Dangane da tsari tsakanin ƙarshen layin gaba (FEOL) da ƙarshen layin baya (BEOL), ana iya raba tsarin TSV zuwa hanyoyin masana'antu guda uku, wato, ta farko (ViaFirst), ta tsakiya (Via Middle) da ta hanyar ƙarshe (Via Last), kamar yadda aka nuna a cikin adadi.
1. Ta hanyar etching
Tsarin ta hanyar etching shine mabuɗin don ƙirƙirar tsarin TSV. Zaɓin tsarin etching mai dacewa zai iya inganta ingantaccen ƙarfin injiniya da kaddarorin lantarki na TSV, da ƙari da alaƙa da amincin na'urori masu girma uku na TSV.
A halin yanzu, akwai manyan TSV guda huɗu na al'ada ta hanyar aiwatar da etching: Deep Reactive Ion Etching (DRIE), rigar etching, ɗaukar hoto mai taimakon electrochemical etching (PAECE) da hakowa na Laser.
(1) Deep Reactive Ion Etching (DRIE)
Deep reactive ion etching, kuma aka sani da DRIE tsari, shi ne mafi yawan amfani da TSV etching tsari, wanda aka yafi amfani da su gane TSV via Tsarin da babban al'amari rabo. Tsarin etching na al'ada na al'ada na al'ada na iya cimma zurfin etching na microns da yawa, tare da ƙarancin etching da ƙarancin zaɓin abin rufe fuska. Bosch ya yi daidaitattun gyare-gyaren tsari akan wannan tushen. Ta amfani da SF6 azaman iskar gas mai amsawa da sakewa C4F8 iskar gas yayin aiwatar da etching azaman kariyar wucewa ga bangon gefe, ingantaccen tsarin DRIE ya dace da etching babban al'amari rabo vias. Saboda haka, ana kuma kiran shi tsarin Bosch bayan mai ƙirƙira shi.
Hoton da ke ƙasa hoto ne na babban yanayin rabo ta hanyar ƙera tsarin DRIE.
Kodayake ana amfani da tsarin DRIE sosai a cikin tsarin TSV saboda kyakkyawan ikon sarrafa shi, rashin lahaninsa shine rashin daidaituwar bangon bangon ba shi da kyau kuma za a sami lahani na wrinkle mai siffar scallop. Wannan lahani yana da mahimmanci yayin da aka haɗa babban rabo ta hanyar vis.
(2) Jikin etching
Wet etching yana amfani da haɗin abin rufe fuska da etching sinadarai don ƙyale ta cikin ramuka. Maganin etching da aka fi amfani da shi shine KOH, wanda zai iya ƙulla matsayi a kan silin da abin rufe fuska ba shi da kariya, don haka ya samar da tsarin da ake so ta hanyar rami. Rigar etching shine farkon tsarin etching ta cikin rami. Tun da matakan tsari da kayan aikin da ake buƙata suna da sauƙi, ya dace da yawan samar da TSV a ƙananan farashi. Duk da haka, na'urar etching ta sinadarai ta ƙayyade cewa ramin da aka kafa ta wannan hanyar zai shafi yanayin daɗaɗɗen siliki na siliki, wanda ya sa kullun ta cikin rami ba a tsaye ba amma yana nuna wani abu mai haske na sama da kunkuntar kasa. Wannan lahani yana iyakance aikace-aikacen rigar etching a masana'antar TSV.
(3) Etching electrochemical etching (PAECE) mai ɗaukar hoto
Babban ka'idar etching electrochemical-hoto (PAECE) ita ce amfani da hasken ultraviolet don haɓaka haɓaka nau'ikan nau'ikan ramukan lantarki, ta haka yana haɓaka aikin etching electrochemical. Idan aka kwatanta da tsarin DRIE da ake amfani da shi da yawa, tsarin PAECE ya fi dacewa don ƙaddamar da babban rabo mai girma ta hanyar ramuka fiye da 100: 1, amma rashin amfaninsa shine ikon sarrafa zurfin etching ya fi DRIE rauni, kuma fasahar sa na iya yin rauni. yana buƙatar ƙarin bincike da haɓaka tsari.
(4) Laser hakowa
Ya bambanta da hanyoyin uku na sama. Hanyar hakowa Laser hanya ce ta zahiri kawai. Yafi amfani da high-makamashi Laser sakawa a iska mai guba don narke da ƙafe da substrate abu a cikin ƙayyadadden yanki don jiki gane ta-rami yi na TSV.
The ta-rami kafa ta Laser hakowa yana da babban al'amari rabo da sidewall ne m a tsaye. Duk da haka, tun da hakowa Laser a zahiri yana amfani da dumama gida don samar da ramin ramin, bangon rami na TSV zai sami mummunan lalacewa ta hanyar lalatawar thermal kuma ya rage dogaro.
2. Tsarin ƙaddamarwa Layer Layer
Wani mabuɗin fasaha don kera TSV shine tsarin ƙaddamar da layin layi.
Ana aiwatar da tsarin jigon layin layi bayan an cire ramin. Layin layin da aka ajiye gabaɗaya oxide ne kamar SiO2. Layin layin yana tsakanin madugu na ciki na TSV da substrate, kuma galibi yana taka rawar keɓewar ɗigon DC na yanzu. Baya ga ajiye oxide, shinge da yadudduka iri ana kuma buƙatar don cika shugaba a cikin tsari na gaba.
Dole ne Layer ɗin da aka ƙera ya cika waɗannan buƙatu guda biyu masu zuwa:
(1) rushewar wutar lantarki na rufin rufi ya kamata ya dace da ainihin buƙatun aiki na TSV;
(2) ɗakunan da aka ajiye suna da daidaituwa sosai kuma suna da kyau adhesion ga juna.
Hoton da ke gaba yana nuna hoton layin layin da aka ajiye ta hanyar haɓakar ƙwayar ƙwayar cuta ta plasma (PECVD).
Ana buƙatar daidaita tsarin ƙaddamarwa daidai da hanyoyin TSV daban-daban. Don tsarin gaba ta hanyar-rami, ana iya amfani da tsarin ƙaddamar da zafin jiki don inganta ingancin Layer oxide.
Yawan zafin jiki na yau da kullun na iya dogara ne akan tetraethyl orthosilicate (TEOS) haɗe tare da tsarin iskar oxygenation na thermal don samar da ingantacciyar madaidaicin insulating Layer SiO2. Don tsaka-tsakin tsaka-tsaki da baya ta hanyar rami, tun lokacin da aka kammala aikin BEOL a lokacin ƙaddamarwa, ana buƙatar hanyar ƙananan zafin jiki don tabbatar da dacewa da kayan BEOL.
A ƙarƙashin wannan yanayin, yakamata a iyakance yawan zafin jiki zuwa 450 °, gami da amfani da PECVD don saka SiO2 ko SiNx azaman rufin rufi.
Wata hanyar gama gari ita ce a yi amfani da jigon atomic Layer ajiya (ALD) don saka Al2O3 don samun Layer insulating.
3. Tsarin cika ƙarfe
Ana aiwatar da tsarin cikawar TSV nan da nan bayan tsarin jigilar layin layi, wanda shine wata babbar fasahar da ke ƙayyade ingancin TSV.
Kayayyakin da za a iya cika sun hada da doped polysilicon, tungsten, carbon nanotubes, da dai sauransu dangane da tsarin da ake amfani da su, amma mafi yawan al'ada har yanzu ana amfani da tagulla, saboda tsarinsa ya balaga kuma ƙarfin wutar lantarki da yanayin zafi yana da girma.
Dangane da bambance-bambancen rarraba wutar lantarki ta hanyar rami, ana iya raba shi zuwa hanyoyin subconformal, conformal, superconformal da hanyoyin samar da lantarki na ƙasa, kamar yadda aka nuna a cikin adadi.
Subconformal electroplating aka yafi amfani a farkon mataki na TSV bincike. Kamar yadda aka nuna a cikin Hoto (a), Cu ions da aka samar ta hanyar lantarki suna tattara su a sama, yayin da ƙasa ba ta da isasshen ƙarfi, wanda ke haifar da ƙimar wutar lantarki a saman ramin ta sama fiye da na sama. Sabili da haka, za a rufe saman ramin a gaba kafin a cika shi gaba daya, kuma za a sami babban rami a ciki.
Ana nuna zane-zane da hoto na hanyar daidaita wutar lantarki a cikin Hoto (b). Ta hanyar tabbatar da kariyar kariyar Cu ions, ƙimar wutar lantarki a kowane matsayi a cikin ramin ramin ɗaya ne, don haka kawai za a bar kubu a ciki, kuma ƙarar da ba ta da tushe ya fi na tsarin lantarki na subconformal, don haka. ana amfani da shi sosai.
Don ci gaba da samun sakamako mai cikawa mara amfani, an gabatar da hanyar superconformal electroplating don inganta hanyar daidaita wutar lantarki. Kamar yadda aka nuna a cikin Hoto (c), ta hanyar sarrafa wadatar Cu ions, ƙimar cikawa a ƙasa ya ɗanɗana sama da wancan a wasu wurare, ta haka yana haɓaka matakin gradient na ƙimar cikawa daga ƙasa zuwa sama don kawar da gaba ɗaya gefen hagu. ta hanyar daidaitaccen tsarin lantarki, ta yadda za a cimma cikakkiyar cikawar ƙarfe mara amfani.
Ana iya la'akari da hanyar samar da wutar lantarki ta ƙasa a matsayin lamari na musamman na babbar hanyar da ta dace. A wannan yanayin, ƙimar wutar lantarki banda ƙasa an danne shi zuwa sifili, kuma kawai ana aiwatar da wutar lantarki daga ƙasa zuwa sama. Baya ga fa'idar da ba ta da amfani ta hanyar daidaita wutar lantarki, wannan hanya kuma tana iya rage yawan lokacin lantarki yadda ya kamata, don haka an yi nazari sosai a cikin 'yan shekarun nan.
4. fasahar aiwatar da RDL
Tsarin RDL fasaha ce ta asali da ba makawa a cikin tsarin marufi mai girma uku. Ta wannan tsari, ana iya ƙera haɗin haɗin ƙarfe a ɓangarorin biyu na ƙasa don cimma manufar sake rarraba tashar jiragen ruwa ko haɗin kai tsakanin fakiti. Don haka, ana amfani da tsarin RDL sosai a cikin fan-in-fan-out ko tsarin marufi na 2.5D/3D.
A cikin aikin gina na'urori masu girma uku, tsarin RDL yawanci ana amfani da shi don haɗa haɗin TSV don gane nau'ikan na'urori masu girma dabam uku.
A halin yanzu akwai manyan hanyoyin RDL guda biyu. Na farko yana dogara ne akan polymers masu ɗaukar hoto kuma an haɗa su tare da tsarin lantarki na jan karfe da etching; Ana aiwatar da ɗayan ta hanyar amfani da tsarin Cu Damascus wanda aka haɗa tare da PECVD da tsarin polishing na injiniya (CMP).
Mai zuwa zai gabatar da manyan hanyoyin aiwatar da waɗannan RDL guda biyu bi da bi.
Ana nuna tsarin RDL akan polymer mai ɗaukar hoto a cikin adadi na sama.
Da farko, ana lulluɓe manne na PI ko BCB a saman wafer ta hanyar juyawa, kuma bayan dumama da warkewa, ana amfani da tsarin hoto don buɗe ramuka a matsayin da ake so, sannan a yi etching. Na gaba, bayan cire photoresisist, Ti da Cu suna sputtered a kan wafer ta hanyar jiki tururi tsari (PVD) a matsayin shãmaki Layer da iri Layer, bi da bi. Bayan haka, ana kera Layer na farko na RDL akan titin Ti/C da aka fallasa ta hanyar haɗa photolithography da hanyoyin sarrafa wutar lantarki, sannan an cire mai ɗaukar hoto kuma an cire wuce haddi na Ti da Cu. Maimaita matakan da ke sama don samar da tsarin RDL mai yawan Layer. Wannan hanya a halin yanzu an fi amfani da ita a cikin masana'antu.
Wata hanya don kera RDL ta dogara ne akan tsarin Cu Damascus, wanda ya haɗu da ayyukan PECVD da CMP.
Bambanci tsakanin wannan hanyar da tsarin RDL dangane da polymer photosensitive shine cewa a farkon matakin kera kowane Layer, ana amfani da PECVD don saka SiO2 ko Si3N4 azaman insulating Layer, sa'an nan kuma an samar da taga akan rufin insulating ta hanyar photolithography. ion etching reactive, da Ti/Cu barrier/seed Layer da madugu jan karfe ana sputtered bi da bi, sa'an nan da madugu Layer na bakin ciki zuwa ga kauri da ake bukata ta CMP tsari, wato, Layer na RDL ko ramuka yana samuwa.
Hoto na gaba shine zane mai tsari da hoto na sashin giciye na RDL mai yawan Layer da aka gina bisa tsarin Cu Damascus. Ana iya lura da cewa an fara haɗa TSV zuwa Layer V01 ta ramuka, sa'an nan kuma an jera shi daga ƙasa zuwa sama bisa tsari na RDL1, Layer V12, da RDL2.
Kowane Layer na RDL ko ta ramuka ana kera shi a jere bisa ga hanyar da ke sama.Tunda tsarin RDL yana buƙatar amfani da tsarin CMP, farashin masana'anta ya fi na tsarin RDL da ya dogara akan polymer mai ɗaukar hoto, don haka aikace-aikacen sa yana da ɗan ƙaramin ƙarfi.
5. IPD fasaha fasaha
Don kera na'urori masu girma uku, ban da haɗa kai tsaye akan guntu akan MMIC, tsarin IPD yana ba da wata hanyar fasaha mai sassauƙa.
Integrated m na'urorin, kuma aka sani da IPD tsari, hade duk wani hade m na'urorin ciki har da on-chip inductor, capacitors, resistors, balun converters, da dai sauransu. a kira a sassauƙa bisa ga buƙatun ƙira.
Tun da a cikin tsarin IPD, ana kera na'urori masu amfani da kai tsaye a kan allon canja wuri, tsarin tafiyar da shi ya fi sauƙi kuma maras tsada fiye da haɗin kan guntu na ICs, kuma ana iya samar da taro a gaba a matsayin ɗakin karatu na na'ura.
Don TSV masana'anta m na'ura mai girma uku, IPD na iya yadda ya kamata ya daidaita nauyin farashi na tsarin marufi uku ciki har da TSV da RDL.
Baya ga fa'idodin farashi, wani fa'idar IPD shine babban sassauci. Ɗaya daga cikin sassaucin ra'ayi na IPD yana nunawa a cikin hanyoyin haɗin kai daban-daban, kamar yadda aka nuna a cikin hoton da ke ƙasa. Baya ga mahimman hanyoyin guda biyu na haɗa IPD kai tsaye a cikin madaidaicin fakiti ta hanyar tsarin juyawa kamar yadda aka nuna a cikin Hoto (a) ko tsarin haɗin kai kamar yadda aka nuna a cikin Hoto (b), za a iya haɗa wani Layer na IPD akan Layer ɗaya. na IPD kamar yadda aka nuna a Figures (c)-(e) don cimma faffadan kewayon haɗaɗɗun na'urori masu wucewa.
A lokaci guda, kamar yadda aka nuna a cikin Hoto (f), ana iya ƙara amfani da IPD azaman allon adaftar don binne guntu da aka haɗa kai tsaye a kai don gina tsarin marufi mai girma kai tsaye.
Lokacin amfani da IPD don gina na'urorin wucewa masu girma uku, ana iya amfani da tsarin TSV da tsarin RDL. Matsakaicin tsari iri ɗaya ne da na sama da aka ambata a sama hanyar haɗin kai akan guntu, kuma ba za a maimaita ba; Bambanci shine cewa tun lokacin da aka canza abu na haɗin kai daga guntu zuwa allon adaftan, babu buƙatar yin la'akari da tasirin tsarin marufi uku akan yanki mai aiki da haɗin haɗin gwiwa. Wannan yana ƙara haifar da wani maɓalli na IPD: nau'ikan kayan aikin ƙasa za a iya zaɓa cikin sassauƙa gwargwadon buƙatun ƙira na na'urori masu wucewa.
The substrate kayan samuwa ga IPD ne ba kawai na kowa semiconductor substrate kayan kamar Si da GaN, amma kuma Al2O3 tukwane, low-zazzabi / high-zazzabi co-kora tukwane, gilashin substrates, da dai sauransu Wannan alama yadda ya kamata fadada zane sassauci na m. na'urorin da aka haɗa ta IPD.
Misali, tsarin inductor mai girma uku da aka haɗa ta IPD na iya amfani da ƙaramin gilashi don inganta aikin inductor yadda ya kamata. Ya bambanta da ra'ayi na TSV, ramukan da aka yi a kan gilashin gilashi kuma ana kiran su ta hanyar gilashin (TGV). Hoton inductor mai girma uku da aka kera bisa tsarin IPD da TGV ana nuna shi a cikin hoton da ke ƙasa. Tun da resistivity na gilashin substrate ya fi na al'ada semiconductor kayan kamar Si, da TGV uku-girma inductor yana da mafi ingancin rufi Properties, da saka asara lalacewa ta hanyar substrate parasitic sakamako a high mitoci ne da yawa karami fiye da na na inductor mai girma uku na TSV na al'ada.
A daya hannun, karfe-insulator-karfe (MIM) capacitors kuma za a iya kerarre a kan gilashin substrate IPD ta wani bakin ciki film jita-jita tsari, da interconnected tare da TGV uku-girma inductor don samar da uku-girma m tace tsarin. Sabili da haka, tsarin IPD yana da faffadan yuwuwar aikace-aikace don haɓaka sabbin na'urori masu ma'ana masu girma uku.
Lokacin aikawa: Nuwamba-12-2024