Ana buƙatar ɗaruruwan matakai don juya awafera cikin wani semiconductor. Ɗaya daga cikin mahimman matakai shineetching- wato, sassaƙa kyawawan tsarin kewayawa a kanwafer. Nasarar daetchingTsarin ya dogara da sarrafa mabambanta daban-daban a cikin kewayon rarraba saiti, kuma kowane kayan aikin etching dole ne a shirya don aiki ƙarƙashin ingantattun yanayi. Injiniyoyin aikin mu na etching suna amfani da ingantacciyar fasahar kere kere don kammala wannan cikakken tsari.
Cibiyar Labarai ta SK Hynix ta yi hira da membobin Icheon DRAM Front Etch, Middle Etch, da Ƙarshen Etch ƙungiyoyin fasaha don ƙarin koyo game da aikinsu.
Etch: Tafiya zuwa Inganta Haɓakawa
A masana'antar semiconductor, etching yana nufin ƙirar sassaƙa akan siraran fina-finai. Ana fesa ƙirar ta amfani da plasma don samar da jita-jita na ƙarshe na kowane mataki na tsari. Babban manufarsa ita ce gabatar da madaidaicin tsari daidai da shimfidar wuri da kuma kula da sakamako iri ɗaya a ƙarƙashin kowane yanayi.
Idan matsaloli sun faru a cikin tsarin ajiya ko tsarin hoto, ana iya magance su ta hanyar fasahar etching (Etch). Duk da haka, idan wani abu ya yi kuskure a lokacin aikin etching, ba za a iya canza yanayin ba. Wannan shi ne saboda ba za a iya cika abu ɗaya a cikin wurin da aka zana ba. Don haka, a cikin tsarin masana'antar semiconductor, etching yana da mahimmanci don tantance yawan amfanin ƙasa da ingancin samfur.
Tsarin etching ya ƙunshi matakai takwas: ISO, BG, BLC, GBL, SNC, M0, SN da MLM.
Na farko, ISO (Warewa) matakin etches (Etch) silicon (Si) akan wafer don ƙirƙirar yanki mai aiki. Matsayin BG (Buried Gate) yana samar da layin adireshin layi (Layin Kalma) 1 da ƙofar don ƙirƙirar tashar lantarki. Bayan haka, matakin BLC (Bit Line Contact) yana haifar da haɗi tsakanin ISO da layin adireshin shafi (Bit Line) 2 a cikin yankin tantanin halitta. Matakin GBL (Peri Gate+Cell Bit Line) zai ƙirƙiri layin adireshin ginshiƙi na salula da ƙofar da ke gefen 3.
Matsayin SNC (Storage Node Contract) yana ci gaba da haifar da haɗin kai tsakanin yanki mai aiki da kullin ajiya 4. Daga bisani, matakin M0 (Metal0) ya samar da wuraren haɗin haɗin S / D na gefe (Storage Node) 5 da haɗin haɗin gwiwa. tsakanin layin adireshin shafi da kullin ajiya. Matsayin SN (Storage Node) yana tabbatar da ƙarfin naúrar, kuma matakin MLM (Multi Layer Metal) na gaba yana haifar da samar da wutar lantarki na waje da wayoyi na ciki, kuma an kammala aikin injiniya gabaɗayan etching (Etch).
Ganin cewa masu fasaha na etching (Etch) sune galibi ke da alhakin ƙirar semiconductor, sashen DRAM ya kasu kashi uku: Front Etch (ISO, BG, BLC); Etch ta tsakiya (GBL, SNC, M0); Ƙarshen Etch (SN, MLM). Hakanan ana rarraba waɗannan ƙungiyoyi bisa ga matsayin masana'anta da matsayin kayan aiki.
Matsayin masana'anta suna da alhakin sarrafawa da haɓaka hanyoyin samar da naúrar. Matsayin masana'anta suna taka muhimmiyar rawa wajen haɓaka yawan amfanin ƙasa da ingancin samfur ta hanyar sarrafawa mai canzawa da sauran matakan inganta samarwa.
Matsayin kayan aiki suna da alhakin sarrafawa da ƙarfafa kayan aikin samarwa don guje wa matsalolin da za su iya faruwa a lokacin aikin etching. Babban alhakin matsayi na kayan aiki shine tabbatar da ingantaccen aikin kayan aiki.
Kodayake alhakin ya bayyana a fili, duk ƙungiyoyi suna aiki zuwa manufa ɗaya - wato, don sarrafawa da inganta hanyoyin samar da kayayyaki da kayan aiki masu dangantaka don inganta yawan aiki. Don wannan, kowace ƙungiya tana ba da ra'ayi na raba nasarorin da suka samu da wuraren haɓakawa, kuma suna ba da haɗin kai don haɓaka ayyukan kasuwanci.
Yadda za a tinkari kalubalen fasahar kere-kere
SK Hynix ya fara samar da tarin samfuran 8Gb LPDDR4 DRAM don tsarin aji na 10nm (1a) a cikin Yuli 2021.
Siffofin da'irar ƙwaƙwalwar ajiyar semiconductor sun shiga zamanin 10nm, kuma bayan haɓakawa, DRAM ɗaya na iya ɗaukar kusan sel 10,000. Sabili da haka, ko da a cikin tsarin etching, gefen tsari bai isa ba.
Idan rami da aka kafa (Rami) 6 ya yi ƙanƙanta, yana iya bayyana “ba a buɗe ba” kuma ya toshe ƙananan ɓangaren guntu. Bugu da ƙari, idan ramin da aka kafa ya yi girma sosai, "gada" na iya faruwa. Lokacin da rata tsakanin ramuka biyu bai isa ba, "gado" yana faruwa, yana haifar da matsalolin mannewa juna a matakai na gaba. Kamar yadda semiconductors ke ƙara haɓakawa, kewayon ƙimar girman rami yana raguwa a hankali, kuma waɗannan haɗarin za a kawar da su a hankali.
Don magance matsalolin da ke sama, ƙwararrun fasahar etching sun ci gaba da inganta tsarin, gami da gyaggyara tsarin girke-girke da APC7 algorithm, da gabatar da sabbin fasahohin etching kamar ADCC8 da LSR9.
Yayin da bukatun abokin ciniki ya zama daban-daban, wani kalubale ya fito - yanayin samar da kayayyaki da yawa. Don saduwa da irin waɗannan buƙatun abokin ciniki, ingantaccen yanayin tsari na kowane samfur yana buƙatar saita shi daban. Wannan ƙalubale ne na musamman ga injiniyoyi domin suna buƙatar yin fasahar samar da yawan jama'a ta dace da buƙatun da aka kafa da kuma yanayi daban-daban.
Don haka, injiniyoyin Etch sun gabatar da fasaha na "APC offset" 10 don sarrafa abubuwa daban-daban dangane da samfuran asali (Mahimman samfuran), kuma sun kafa kuma sun yi amfani da "T-index system" don sarrafa kayayyaki daban-daban. Ta hanyar waɗannan ƙoƙarin, an ci gaba da inganta tsarin don biyan bukatun samar da kayayyaki da yawa.
Lokacin aikawa: Yuli-16-2024